A driving circuit for a voltage driving type semiconductor switching device such as an FET or IGBT includes a switching device (ON-driving device) for applying an ON-voltage to the gate of the switching device to be driven (driving target device) and a switching device (OFF-driving device) for applying an OFF-voltage to its gate. The ON/OFF state of the driving target device is controlled by turning on one of the ON-driving device and the OFF-driving device and turning off the other.
In this type of gate driving circuit, it is desired to reduce switching loss and electromagnetic noise, which occur at the time of switching of the driving target device. As one method, the value of a resistor (gate resistor) connected to the gate or the gate current is finely adjusted during a period (switching period) required for turning on or turning off the driving target device (JP 2001-314075A).
The switching operation of the voltage driving type semiconductor switching device can be understood as a charging/discharging process of parasitic capacitance occurring between the gate and emitter (gate and source). Accordingly, when the gate resistor is made small, the current variation rate of a gate current becomes large, and a time required for charging/discharging the parasitic capacitance of the gate becomes short. Accordingly, the switching loss is reduced but the noise is increased. On the other hand, when the gate resistor is made large, although the noise is reduced, the switching loss is increased.
By using this relation, driving is performed such that the gate resistor is first set to a low resistance value, so that the voltage between the collector and emitter quickly rises, that is, high-speed switching is made. Then, when the voltage between the collector and emitter reaches a specified value, the gate resistor is switched to a high resistance value, so that the variation rate of the voltage or current is suppressed.
However, the switching period of the voltage driving type semiconductor switching device used as the driving target device is normally several hundreds nanoseconds (ns) or less. In the above conventional gate driving circuit of JP 2001-314075A, the resistance value must be switched at good timing in such a very short switching period.
Accordingly, the conventional device must be constructed by using a high speed operating element to make the gate resistance value variable, and a high accuracy sensor to detect a high voltage. Thus, the device becomes complicated and expensive. Further, the control is difficult since there is no margin in the timing of the control. Besides, since the conventional device uses the gate resistor, it is impossible to avoid the trade-off between the noise reduction and the switching loss reduction (high-speed switching). Still further, a great improvement cannot be expected, and a conduction loss at the gate resistor is increased when the frequency of switching of the driving target device is further increased.
On the other hand, US 2005/0001659A1 (JP 2005-39988A) proposes a gate driving circuit 100 constructed as shown in FIG. 13. In this circuit 100, power is supplied from a DC power source 103 to a reactor 105 through a bridge circuit 101 including four switching devices 101a to 101d, and one end of the reactor 105 is connected to a gate of a driving target device SW.
In this gate driving circuit 100, as shown in FIG. 14, when the driving target device SW is turned on (switching from the OFF state to the ON state) or turned off (switching from the ON state to the OFF state), a reactor current Ir is made to flow through the reactor 105 via the bridge circuit 101 during a set specific period (T11 to T12, T15 to T16). When the reactor current Ir increases to a necessary magnitude (timing T12, T16), the connection state of the bridge circuit 101 is switched so that the reactor 105 and parasitic capacitance of the gate of the driving target device SW form a resonant circuit. Thus, the gate current Ig is not gradually increased after turn-on or turn-off, but the gate current Ig equal to the reactor current Ir flows at the same time as the turn-on or turn-off. Further, the gate current Ig flowing through the resonant circuit does not quickly change, and accordingly, the reduction (high-speed switching) of the switching loss and the reduction of noise can be made compatible with each other.
However, in this gate driving circuit 100, when the interval between the turn-on and the turn-off (interval between T12 and T16) becomes short, the reactor current Ir with a required magnitude cannot be made to flow before the next turn-on or turn-off, and the foregoing effect cannot be sufficiently obtained.
That is, in the gate driving circuit 100, the direction of the reactor current Ir flowing through the reactor 105 is opposite between the turn-on time and the turn-off time. Therefore, when the reactor current Ir for the next turn-on or turn-off is started to flow (when the timings T14 and T15 are reversed) before the reactor current Ir is returned to zero, the reactor current Ir cannot be increased to the required magnitude before the timing T12 or T16 of the turn-on or turn-off.